1. Field of the Invention
The present invention relates to a bus arbiter.
2. Description of the Related Art
In a first example of a conventional bus arbiter, since the bus arbiter does not normally operate for a request to write in/read from an address for which a corresponding device is absent, an apparatus for generating an address has the function of prohibiting a request to write in/read from an address outside a set address region, for example, by referring to an address map within the system.
In a second example of a conventional bus arbiter also operating as a DRAM (dynamic random access memory) controller as shown in FIG. 13, the system is controlled by a CPU 300 having a data-bus width of 16 bits, and programs to be executed by the CPU 300 are stored in a ROM (read-only memory) 400. A bus arbiter 500 also operating as a DRAM controller arbitrates accesses of the CPU 300 and a DMA (direct memory access) controller 800 to DRAM's 600 and 700. Each of the DRAM's 600 and 700 has a capacity of 4M bits and a data bus width of 16 bits. The DRAM's 600 and 700 store upper words and lower words, respectively. The DMA controller 800 has a data bus width of 32 bits.
There are shown signals 311-338 between respective blocks. Reference numeral 311 represents a chip select signal ROMCS for the ROM 400. Reference numeral 312 represents a CPU data bus CPU.sub.-- D [15:0] having a bus width of 16 bits. Reference numeral 313 represents a CPU address bus CPU.sub.-- A [23:1] having a bus width of 23 bits. Reference numerals 314, 315, 316, 317, 318, 319, and 320 represent a reset signal Reset, a system clock signal Clock, an address strobe signal AS, a read signal RD, an upper-byte write signal UWR, a lower-byte write signal LWR, and a wait signal Wait, respectively.
Reference numeral 321 represents a DRAM address bus DRAM.sub.-- A [8:0] having a bus width of 9 bits. Reference numeral 322 represents an upper-word DRAM data bus DRAM.sub.-- D.sub.-- U [15:0] having a bus width of 16 bits. Reference numerals 323, 324, 325, 326, and 327 represent an upper-word DRAM row-address strobe signal RAS.sub.-- U, an upper-word DRAM upper-byte column-address strobe signal UCAS.sub.-- U, an upper-word DRAM lower-byte column-address strobe signal LCAS.sub.-- U, an upper-word DRAM write signal WE.sub.-- U, and an upper-word DRAM read signal OE.sub.-- U, respectively.
Reference numeral 328 represents a lower-word DRAM data bus DRAM.sub.-- D.sub.-- L having a bus width of 16 bits. Reference numerals 329, 330, 331, 332, and 333 represent a lower-word DRAM row-address strobe signal RAS.sub.-- L, a lower-word DRAM upper-byte column-address strobe signal UCAS.sub.-- L, a lower-word DRAM lower-byte column-address strobe signal LCAS.sub.-- L, a lower-word DRAM write signal WE.sub.-- L, and a lower-word DRAM read signal OE.sub.-- L, respectively.
Reference numeral 334 represents a DMA data bus DMA.sub.-- D [31:0] having a bus width of 32 bits. Reference numeral 335 represents a DMA address bus DMA A [23:2] having a bus width of 22 bits. Reference numerals 336, 337, and 338 represent a DMA request signal DMA.sub.-- Req, a DMA direction signal DMA.sub.-- Dir, and a DMA acknowledge signal DMA.sub.-- Ack, respectively.
A signal CPU.sub.-- A [0] is absent on the CPU address bus CPU.sub.-- A [23:1], because the CPU 300 has the upper-byte write signal UWR and the lower-byte write signal LWR, and therefore address assignment in units of a byte is unnecessary. A signal DMA.sub.-- A [1:0] is absent on the DMA address bus DMA.sub.-- A [23:2], because in this case, the data width of the DMA controller 800 is 32 bits, and therefore address assignment in units of a byte and in units of a word is unnecessary. The DRAM address bus DRAM.sub.-- A [8:0] comprises only 9 bits, because in this case, the row address and the column address of the DRAM each comprise 9 bits.
FIG. 14 is an address map for the units shown in FIG. 13. The address space of the CPU 300 comprises 0H--FFFFFFH, i.e., 16 M bytes. The addresses 0H--7FFFFFH and 800000H--8FFFFFH are allocated to the ROM 400 and to the RAM's 600 and 700, respectively. The address 900000H and the succeeding addresses are allocated to a register of the DMA controller 800, an input/output register (not shown in FIG. 3), and an internal register of the CPU 300.
The CPU 300 executes processing in accordance with a program stored in the ROM 400, and accesses the ROM 400 by the signal ROMCS and by bits between the 22nd bit and the 1st bit on the bus CPU.sub.-- A [23:1]. Accesses from the CPU 300 and the DMA controller 800 to the DRAM's 600 and 700 are performed via the bus arbiter and DRAM controller 500.
FIG. 15 is a flowchart illustrating the operation of the bus arbiter and DRAM controller 500 during an access by the CPU 300. If the CPU 300 accesses the region of the ROM 400, and an access from the DMA controller 800 is absent, i.e., if the CPU.sub.-- A [23:1] indicates 0H--7FFFFFH indicating the region of the ROM, and the DMA or the DMA.sub.-- Req is not asserted, as results of determination in steps S101 and S102, then, in step S103, CAS-Before-RAS refreshing as shown in the timing chart of FIG. 16 is performed. More specifically, the signals UCAS.sub.-- U, LCAS.sub.-- U, UCAS.sub.-- L and LCAS.sub.-- L are asserted, and then, the signals RAS.sub.-- U and RAS.sub.-- L are asserted.
As described above, the bus arbiter and DRAM controller 500 has a CAS-Before-RAS refreshing function. Usually, the DRAM is required to be refreshed at a frequency equal to or greater than a specified time interval. Hence, the refreshing time interval is monitored by a timer. If the next refreshing operation is not generated for a predetermined time period after a refreshing operation, a refreshing operation is performed by forcedly interrupting the operation of the CPU 300.
Processing from step S104 to step S137 is an access to the RAM region. Accordingly, in step S104, it is determined if an address between 800000H and 8FFFFFH of the RAM region is indicated. If the result of the determination in step S104 is affirmative, the process proceeds to step S105, where a signal CPU.sub.-- A [19:10] is output to the bus DRAM.sub.-- A [8:0] as a row address. Then, in step S106, the fall of a clock pulse is detected. In step S107, it is determined whether a signal CPU.sub.-- A [1] is 0 or 1, i.e., whether the DRAM 600 for upper words or the DRAM 700 for lower words is to be accessed. If the DRAM 600 is to be accessed, then, in step S108, the signal RAS.sub.-- U is asserted. If the DRAM 700 is to be accessed, the signal RAS.sub.-- L is asserted.
Then, in step S110 or step S111, the rise of a clock pulse is detected. Then, in step S112 or step S113, it is determined whether a reading operation or a writing operation is to be performed. In the case of a reading operation, the signal OE.sub.-- U is asserted in step S116 in the case of an upper word, and the signal OE.sub.-- L is asserted in step S117 in the case of a lower word.
In the case of a writing operation, the signal WE.sub.-- L is asserted in step S116 in the case of an upper word, and the signal WE.sub.-- L is asserted in step s117 in the case of a lower word. Then, in step S118 or step S119, a signal CPU.sub.-- A [9:2] is output to the bus DRAM.sub.-- A [8:0] as a column address.
Then, in step S120 or S121, the rise of a clock pulse is detected. In step S122 or step S123, it is determined if a reading operation is to be performed. In the case of a reading operation, the signal UCAS.sub.-- U or LCAS.sub.-- U is asserted in step S124 in the case of an upper word, and the signal UCAS.sub.-- L or LCAS.sub.-- L is asserted in step S125 in the case of a lower word.
If a reading operation is not be performed, then, in step S126 or S127, it is determined if an operation to write an upper byte is to be performed. In the case of an operation to write an upper byte, the signal UCAS.sub.-- U is asserted in step S128 in the case of an upper word, and the signal UCAS.sub.-- L is asserted in step S129 in the case of a lower word.
Similarly, in step S130 or S131, it is determined if an operation to write a lower byte is to be performed. In the case of an operation to write a lower byte, the signal LCAS.sub.-- U is asserted in step S132 in the case of an upper word, and the signal LCAS.sub.-- L is asserted in step S133 in the case of a lower word.
Then, in steps S134--S136, the rise, the fall and the rise of clock pulses are detected, respectively. Finally, in step S137, all of the signals RAS.sub.-- U, RAS.sub.-- L, UCAS.sub.-- U, LCAS.sub.-- U, UCAS.sub.-- L, LCAS.sub.-- L, OE.sub.-- U, OE.sub.-- L, WE.sub.-- U, and WE.sub.-- L are negated, and the series of processing is terminated.
FIG. 17 is a timing chart illustrating the accessing of the DRAM's 600 and 700 from the DMA controller 800, in the case of reading a long word. The DMA controller 800 sets the signals DMA.sub.-- A [23:2] and DMA.sub.-- Dir for the bus arbiter and DRAM controller 500, and then outputs the signal DMA.sub.-- Req. When the upper 4-bit DMA.sub.-- A [23:2] of the DMA.sub.-- A [23:2] is 8 H, i.e., an address indicating the DRAM, the bus arbiter and DRAM controller 500 outputs the signals RAS.sub.-- U, UCAS.sub.-- U, LCAS.sub.-- U, OE.sub.-- U, RAS.sub.-- L, UCAS.sub.-- L, LCAS.sub.-- L and OE.sub.-- L to cause the DRAM's 600 and 700 to output the signals DRAM.sub.-- D.sub.-- U [15:0] and DRAM.sub.-- D.sub.-- L [15:0], outputs the signals DRAM.sub.-- D.sub.-- U [15:0] and DRAM.sub.-- D.sub.-- L [15:0] as signals DMA.sub.-- D [31:16] and DMA.sub.-- D [15:0], respectively, to the DMA controller 800, and, at the same time, transmits the signal DMA.sub.-- Ack to the DMA controller 800.
In the case of an operation to write a long word, shown in FIG. 18, the DMA controller 800 sets signals DMA.sub.-- A [23:2], DMA.sub.-- D [31:0] and DMA.sub.-- Dir for the bus arbiter and DRAM controller 500, and then outputs the signal DMA.sub.-- Req. When the upper bit DMA.sub.-- A [23:21] of the DMA.sub.-- A [23:2] is 8 H, i.e., an address indicating the DRAM, the bus arbiter and DRAM controller 500 outputs the signals RAS.sub.-- U, UCAS.sub.-- U, LCAS.sub.-- U, WE.sub.-- U, RAS.sub.-- L, UCAS.sub.-- L, LCAS.sub.-- L and WE.sub.-- L, outputs signals DMA.sub.-- D [31:16] and DMA.sub.-- D [15:0] to the buses DRAM.sub.-- D.sub.-- U [15:0] and DRAM.sub.-- D.sub.-- L [15:0], respectively, and, at the same time, transmits the signal DMA.sub.-- Ack to the DMA controller 800.
FIG. 19 is a timing chart for when the CPU 300 accesses the DRAM's 600 and 700, which corresponds to the flowchart shown in FIG. 15.
FIGS. 19, 20, 21, 22, 23, 24, 25 and 26 indicate the cases of reading an upper word, reading a lower word, writing an upper word, writing a lower word, writing an upper word and an upper byte, writing a lower word and an upper byte, writing an upper word and a lower byte, and writing a lower word and a lower byte, respectively.
The bus arbiter and DRAM controller 500 selects whether the DRAM 600 or the DRAM 700 is to be accessed in accordance with the signal CPU.sub.-- A [23:1], the read signal RD, the upper-byte write signal UWR, the lower-byte write signal LWR out-put from the CPU 300, and controls the signals DRAM.sub.-- A [8:0], RAS.sub.-- U, UCAS.sub.-- U, LCAS.sub.-- U, WE.sub.-- U, OE.sub.-- U, RAS.sub.-- L, UCAS.sub.-- L, LCAS.sub.-- L, WE.sub.-- L and OE.sub.-- L.
In the case of a writing operation, the bus arbiter and DRAM controller 500 selects bytes of the buses DRAM.sub.-- D.sub.-- U [15:0] and DRAM.sub.-- D.sub.-- L.sub.-- [15:0] where an upper or lower byte of the bus CPU.sub.-- D [15:0] is to be output. In the case of a reading operation, the bus arbiter and DRAM controller 500 selects one of the signals DRAM.sub.-- D.sub.-- U [15:0] and DRAM.sub.-- D.sub.-- L.sub.-- [15:0] which is to be output to the bus CPU.sub.-- D [15:0].
When an access from the CPU 300 to the DRAM's 600 and 700 and an access from the DMA controller 800 to the DRAM's 600 and 700 are concurrent, if the access from the CPU 300 and the access from the DMA controller 800 have simultaneously occurred, an access having a higher priority order is first processed. When the access from the CPU 300 has occurred during the access from the DMA controller 800, the operation of the CPU 300 is temporarily interrupted by asserting a signal Wait for the CPU 300, and the signal Wait is negated upon completion of the access from the DMA controller 800.
However, in the above-described first conventional example, if a plurality of apparatuses for generating addresses are present, it is necessary to provide a plurality of functions of prohibiting a request an address outside a set address region within the system, resulting in an increase in the circuit scale.
In the above-described second conventional example, since a refreshing operation is performed during an access to the ROM, if the ROM is not accessed for a long time period, and, for example, if the CPU continues to access the DRAM using a block transfer command, the opportunity to refresh the DRAM decreases. Hence, it is necessary to refresh the DRAM by forcedly interrupting the processing by the CPU temporarily, resulting in a decrease in the efficiency of use of the CPU.